1. Field of the Invention
The present invention is generally in the field of electrical circuits and systems. More specifically, the present invention is in the field of driver circuitry utilized in driving power semiconductor devices.
2. Background Art
Gate driver circuitry is implemented in a wide variety of electronic circuits and systems. For example, gate drivers are typically utilized in a switching power converter to control the operation of high side and low side power switches, such as power insulated gate bipolar transistors (IGBTs), or power metal-oxide-semiconductor field-effect transistors (MOSFETs), for example, by charging and discharging the gate capacitance of those power switching devices.
As is well known, energy accumulates in the gate capacitance of a switching is device in the process of switching the device ON, and that energy is subsequently discharged from the gate in the course of switching the device OFF. In a conventional gate driver, the gate driver supply voltage is typically used to charge the switching device gate through a resistive path present due to the internal resistance of the gate driver circuitry in series with an external resistor. As a result, power is dissipated through this resistive path each time the gate is charged. In addition, the energy stored in the gate capacitance is dissipated through the resistive path each time the gate is discharged.
As advances in technology require operation at ever higher switching frequencies, the power loss due to charging and discharging of the switching device gate becomes increasingly problematic. For example, at a switching frequency of approximately 10 kHz, the power loss associated with charging and discharging a single switch may by approximately 1.5 W. Moreover, at higher frequencies, and/or when the switching device die size is increased to reduce conduction losses, thereby increasing the gate capacitance, power loss through the charge and discharge process may increase to several watts.
Thus, there is a need to overcome the drawbacks and deficiencies in the conventional art by providing a gate driver configured to substantially eliminate or significantly reduce power loss during charging and discharging of a power transistor gate.